This invention relates to a semiconductor integrated circuit and more particularly to a circuit for adjusting the output impedance of an output circuit and can be applied to a data output circuit of a semiconductor memory having a programmable impedance control function, for example.
With the improvement of the performance of an MPU (microprocessor), the data transfer speed required in memories is steadily enhanced. The operation frequency of a memory used in an external cache memory, for example, exceeds one hundred MHz.
In order to transfer output data of the semiconductor memory to the MPU in the above frequency range, it becomes necessary to attain matching between the impedance of the output circuit of the memory side and the impedance of the data bus on the board by taking into consideration the signal reflection at the data bus on the board on which the MPU and memory are mounted. With an increase in the operation frequency, the precision of the impedance matching becomes more strict.
Therefore, a function for correcting the deviation of an impedance value from the impedance value set at the time of design of the output circuit of the memory is used. More specifically, if the effective driving ability of the transistor of the output circuit is changed in an environment in which the circuit is actually used owing to variations in the manufacturing process and the temperature, the driving ability of the transistor is adjusted to a desired value by changing the transistor size of the output circuit in the circuit operation to correct the variations.
As an example of a circuit for attaining the above method, a programmable impedance buffer circuit shown in FIG. 5 of ISSCC96 FA9.3: A 300 MHz, 3.3 V 1 Mb SRAM Fabricated in a 0.5 .mu.m CMOS Process is provided and the circuit is briefly explained below.
FIG. 9 Shows the conventional programmable impedance buffer circuit disclosed in the above document.
An SRAM having the programmable impedance buffer circuit has such a function (programmable impedance buffer function) that the size (current driving ability) of an output driving transistor will be automatically changed to attain matching between the output impedance of an output circuit 40 and the impedance of an element RQ when the user externally connects the element RQ having a desired value to an external terminal VZQ as the impedance of an output bus to be connected to an output terminal DQ.
That is, in the SRAM, as a means for changing the size of the output driving transistor, four pull-up side output driving transistors 1Y, 2Y, 4Y, 8Y and four pull-down side output driving transistors 1Z, 2Z, 4Z, 8Z respectively having sizes of 1.times.Wu, 2.times.Wu, 4.times.Wu, 8.times.Wu with respect to the size Wu of a unit transistor are prepared.
As an output impedance evaluation circuit 41, four evaluation transistors 1X, 2X, 4X, 8X having sizes equal to, two times, four times and eight times the size of a unit transistor are prepared, and the size of the evaluation transistor is variably changed by controlling the gates of the four evaluation transistors 1X, 2X, 4X, 8X by use of bits of evaluation control signals A0 to A3 of four bits from a control circuit 42 to selectively control the ON/OFF states of the four evaluation transistors 1X, 2X, 4X, 8X.
The control signals A0 to A3 are changed while monitoring the impedance matching state between the evaluation transistors and the element RQ and the contents of the evaluation control signals A0 to A3 set when the matching is attained are stored.
Control signals D0 to D3 of four bits output from the control circuit 42 at adequate timings based on the contents of the stored evaluation control signals A0 to A3 are subjected to the logical process together with other control signals DOCD, OE in a logic gate circuit 44. The gates of the output driving transistors (1Y, 2Y, 4Y, 8Y; 1Z, 2Z, 4Z, 8Z) are controlled by the signals subjected to the logical process to selectively control the ON/OFF states of the output driving transistors so that the size of the output driving transistor can be changed in a range from 0.times.Wu to 15.times.Wu.
In practice, an offset transistor Y0 which is normally set in the ON state is added to the output driving transistors 1Y, 2Y, 4Y, 8Y and an offset transistor Z0 which is normally set in the ON state is added to the output driving transistors 1Z, 2Z, 4Z, 8Z, and as shown in FIG. 10, 16 stages of sizes can be realized in the unit of the size Wu of the unit transistor in the variable range from the size Won of the offset transistor Y0 or Z0 to the total size (Won+15.times.Wu) of all of the transistors.
Likewise, an offset transistor X0 which is normally set in the ON state is added to the evaluation transistors 1X, 2X, 4X, 8X and 16 stages of sizes can be realized in the unit of the size of the unit transistor in the variable range from the size of the offset transistor X0 to the total size of all of the transistors.
If the number of the output driving transistors (1Y, 2Y, 4Y, 8Y), the number of the output driving transistors (1Z, 2Z, 4Z, 8Z) and the number of bits of the control signals C0 to C3 are expressed by m, the variable number of sizes of the output driving transistors is defined by 2.sup.m, and in this example, it is 2.sup.4 =16.
The value of m is determined by the precision of matching and the range of the impedance to be actually covered by the output circuit 40. That is, the size of the output circuit 40 can be set only to a digital value with the size Wu of the unit transistor set as a minimum step and may be deviated by Wu at maximum from a size corresponding to a desired impedance, and therefore, the size Wu of the minimum step is determined by the impedance matching precision.
Further, since the size of the output driving transistor corresponding to the upper limit of the impedance to be covered is set to the size Won of the offset transistor Y0 or Z0 and the size of the output driving transistor corresponding to the lower limit of the impedance to be covered is set to the size (Won+(2.sup.m -1).times.Wu), the values of Won and m are determined based on these values.
As is clearly understood from the above explanation, it is necessary to increase the number m of bits of the control signals and reduce the size Wu of the minimum step in order to enhance the precision of the impedance matching.
However, if the number m of bits of the control signals is increased, the number of control signals supplied to the output circuit 40 is increased and it is desirable to set the value of m as small as possible from the viewpoint of the circuit design. Therefore, the number m of bits of the control signals is determined (m=4 in the above example) by taking the range of impedance to be covered, matching precision, cost and the like into consideration.
As described above, the size of the output driving transistors necessary for realizing a desired impedance is changed in the unit of specified size Wu, but in practice, the current driving ability of the MOS transistor constituting the output driving transistor determines the impedance and it is roughly determined by W/L (W is the channel width of the MOS transistor and L is the channel length or gate width of the MOS transistor). Therefore, if the gate width L of the output driving transistor is changed, it becomes necessary to change the channel width W of the output driving transistor so as to adjust the impedance.
Generally, the gate width L of the MOS transistor is determined by the manufacturing process of a generation to which it belongs and it is a common practice to use a minimum constant value in a range in which no special problem occurs in the characteristics for constructing circuits.
However, the output driving transistor drives a large load of an external portion of the IC chip and requires a large current driving ability unlike a transistor for driving the gate circuit of an internal portion of the IC chip. Therefore, time in which the output driving transistor permits current flow in the transient state becomes longer than that in the other MOS transistor (MOS transistor in the internal circuit) and deterioration in the reliability due to hot carriers generated during the current flow becomes serious because time for permitting a current to flow is long. Thus, it is general to design the gate width L of the output driving transistor to be longer than the gate width L of the MOS transistor of the internal circuit.
Further, the drain of the output driving transistor is applied with a serge (ESD) due to static electricity applied to the external pin of the IC via the output terminal DQ and it is necessary to increase the gate width L in order to attain a sufficiently high withstand voltage against the ESD.
However, if the gate width L of the MOS transistor is increased, the performance of the MOS transistor is lowered, and particularly, the output driving transistor has a large influence on the performance of the IC chip because the load to be driven is large. As a result, it is important to use the minimum gate width L if no problem of reliability or no influence of ESD occurs.
In practice, however, the influence of the ESD withstand voltage is not clear if it is not evaluated by use of the actual IC chip. This because the ESD withstand voltage is largely dependent on the IC manufacturing process, package, protection circuit and other factors and cannot be previously simulated with high precision as in the circuit characteristic.
The gate width L of the output driving transistor must be often changed from a value previously set at the time of design as the result of evaluation by use of the actual IC chip. The reliability of the MOS transistor can be more clearly predicted based on the data base in comparison with the ESD.
However, the manufacturing process actually used is not necessarily kept unchanged from the process predicted at the time of design and time for permitting the current to flow in the output driving transistor is largely dependent on the output load or the like, it is necessary to effect the evaluation by use of the actual IC chip and the gate width L of the output driving transistor may be corrected in some cases after the design of the IC chip.
In practice, at the time of layout design of the output driving transistor, it is a common practice to make the design in preparation for the change of the gate width L and channel width W and a polysilicon wiring which is used as a gate may be formed so that the width thereof can be changed for the gate width L of the output driving transistor.
However, if the channel width W of the output driving transistor is changed, the widths of the diffusion regions (drain and source regions) will be changed and it is necessary to restart the manufacturing process from the first step, the TAT (Turn-Around Time) becomes extremely long, and the manufacturing lot in which the diffusion regions are already formed becomes useless.
Therefore, a plurality of MOS transistors having different sizes are prepared and option lines or wirings for selectively connecting/disconnecting them by use of aluminum wirings are used to adjust the size of the MOS transistor.
That is, in order to increase the design size (channel width W) of the MOS transistor by 20%, transistors with a size of 1/5 of the design size may be additionally connected in parallel.
Therefore, if a plurality of types of MOS transistors of sizes smaller than the design size of the MOS transistor are prepared, the size of the MOS transistor can be changed. If the total sum of the sizes becomes equal to twice the design size, the gate width L can be changed to approximately twice the original gate width.
The change of the size of the MOS transistor for the programmable impedance buffer circuit as described before is considered. In this case, as described before, it is necessary to prepare MOS transistors having determined sizes such as two times, four times, . . . with the minimum step size Wu used as the unit.
In order to adjust the channel width W of the output driving transistor as described before, it is necessary to prepare a plurality of fine adjustment MOS transistors for each of the MOS transistors so that the size adjustment can be attained at the same ratio for the MOS transistors Z0, 1Z, 2Z, 4Z, 8Z having the sizes Won, Wu, 2.times.Wu, 4.times.Wu, . . . , 2.sup.(m-1) .times.Wu as in the pull-down side output driving transistors shown in FIG. 11, for example.
In this case, if four fine adjustment transistors are used for each of the transistors Z0, 1Z, 2Z, 4Z, 8Z of five types of sizes (Won, Wu, 2.times.Wu, 4.times.Wu, 8.times.Wu), it is necessary to prepare 5.times.4=20 fine adjustment transistors and it requires an extremely large area on the layout.
Further, the minimum step size Wu is a small value, but the size of the fine adjustment transistor is set to a smaller value. If, for example, the circuit shown in FIG. 11 is realized by the manufacturing process of 0.4 .mu.m generation, the minimum step size Wu of the impedance matching transistor becomes approx. 2 .mu.m and the fine adjustment transistor has a size in a range in which the narrow channel effect will occur.
The basic reason for causing the above problem in the conventional output circuit having the programmable impedance buffer function is that the fine adjustment transistors are provided for each of the transistors (transistors having the offset size Won and m different sizes Wu, 2.times.Wu, 4.times.Wu, . . . , 2.sup.(m-1) .times.Wu corresponding to the control signals of m bits) constituting the output driving transistor.
As described above, in a case wherein the conventional semiconductor integrated circuit has the programmable impedance buffer function which makes it possible to adjust the impedance of the output circuit according to the external impedance, there occurs a problem that the matching with respect to the manufacturing process is extremely bad if size adjustment transistors are provided for an output driving transistor in which the gate width L may be changed after the ESD withstand voltage and reliability are evaluated on the actual IC chip after the design.